Conceived for Chip Designers
iNoCs is committed to delivering the best possible quality of results, in the minimum possible time, to chip designers. Our solutions are conceived to interface seamlessly with existing IP cores and back-end flows, and do not require disruptive changes. Provide simple, intuitive inputs - get optimal results.
Today's chips are an ensemble of a large amount of cores - processing elements, memories, accelerators, communication interfaces. When it comes to interconnecting them, and various constraints (bandwidth, congestion, latency, propagation delay, floorplanning) come into play, the expression "design complexity" assumes a concrete meaning.
iNoCs is a provider of technology-leading interconnection IP for ASIC and FPGA based on the breakthrough Network-on-Chip paradigm. This IP portfolio enables seamless on-chip connectivity, compliant with the strictest requirements in bandwidth, latency, power and area.
iNoCs is also a supplier of cutting-edge design tools for Networks-on-Chips. 85% of the chip designs are known to be delivered substantially behind schedule, due to ever-changing constraint iterations and timing closure issues. iNoCs tools greatly contribute to the achievement of design closure and shorten time-to-market, thanks to a smart approach which automatically generates on-chip networks based on application requirements. Design simplicity at its best.