Glossary

- Bandwidth

- Bus

- Intellectual Property (IP) core

- Latency

- Link

- Network Interface (NI)

- Network-on-Chip (NoC)

- Packet

- Multi-Processor System-on-Chip (MPSoC)

- Switch

- Topology

- Transaction

Technology

iNoCs is a leading provider of Network-on-Chip (NoC) technology, in terms of IP portfolio, of design tools, and of design services.

The iNoCs Network-on-Chip IP portfolio is a full solution to instantiate networks, and comprises crucial blocks such as switches, network interfaces with support for multiple IP core protocols, links, frequency adapters, size adapters, etc. With this IP portfolio, it is possible to design networks which feature optimal performance, save energy, and have a minimum area cost. Compared to traditional buses, iNoCs networks provide a scalable amount of bandwidth, feature a lower latency under congestion, and make physical design much easier, thanks to wire serialization and segmentation. Since the iNoCs IP is synchronous, design flows are greatly simplified; several adaptors are provided to tackle multi-clock and GALS chips.

The iNoCs Network-on-Chip tools bring designer productivity to a new level. Instead of tedious, time-consuming and sometimes non-converging exploration approaches, iNoCs tools work the way designers need: given a high-level communication specification, they produce a set of alternatives from which the preferred point (e.g. lowest power, or best performance/area) can be chosen. This flow takes early into account floorplanning constraints, ensuring timing closure and reducing the designer effort even more.

iNoCs is also a provider of Network-on-Chip design services. Whenever a chip is not working due to poor interconnect scalability, our experts can provide a tailored, effective solution based on breakthrough iNoCs technology. We guarantee a more effective interconnection solution delivered in a shorter time.

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