News and Events


Oct 19th, 2017

ArterisIP Acquires iNoCs Software and Associated Intellectual Property Rights
Advances the next round of SoC interconnect innovation with cutting-edge software and algorithms created by iNoCs Systems based on EPFL research
Lausanne, Switzerland (October 19th, 2017) — ArterisIP, the innovative supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today announced that it has acquired exclusive rights to iNoCs’ software, hardware, and associated intellectual property. iNoCs was founded in 2007 by leading researchers in the field of network-on-chip (NoC), Giovanni De Micheli, Luca Benini, Federico Angiolini and Srinivasan Murali, to pioneer the field of topology synthesis for the then emerging NoC interconnect IP market. Antonio Pullini later joined them to bring topology placement expertise. iNoCs has developed exciting concepts, algorithms, and software that address the increasing complexity of deep submicron semiconductor interconnects. With this agreement, ArterisIP will accelerate the adoption of these innovative technologies by implementing them in its extensive product roadmap and making them available to its broad customer base. “iNoCs has developed exciting capabilities in network-on-chip automation and topology synthesis. These capabilities are complementary to ArterisIP cache coherent and main interconnect technologies that have been deployed in over 250 SoCs,” said K. Charles Janac, President and CEO of ArterisIP. “We are delighted to be able to leverage the exciting developments pioneered by iNoCs and to be associated with some of the leading researchers in the field of network-on-chip technology.” “ArterisIP is the commercial leader in network-on-chip interconnect technology so it was natural for us to place the iNoCs software and technology with them,” said Giovanni De Micheli, iNoCs co-founder and Professor and Director of the Institute of Electrical Engineering at EPFL, Lausanne, Switzerland. “With our involvement, ArterisIP will be able to leverage the work done by the iNoCs team in their future generation products, and build upon this technology foundation.” The ArterisIP/iNoCs transaction closed on October 18, 2017. The financial terms were not disclosed. About ArterisIP ArterisIP provides system-on-chip (SoC) interconnect IP to accelerate SoC semiconductor assembly for a wide range of applications from automobiles to mobile phones, IoT, cameras, SSD controllers and servers for customers such as Samsung, Huawei / HiSilicon, Mobileye (Intel), Altera (Intel), and NXP Semiconductors. ArterisIP products include the Ncore cache coherent and FlexNoC non-coherent interconnect IP, as well as optional Resilience Package (functional safety) and PIANO automated timing closure capabilities. ArterisIP is an active contributor to the United States Technical Advisory Group to ISO TC22/SG3/WG16, which develops the ISO 26262 automotive functional safety standard. Customer results obtained by using ArterisIP products include lower power, higher performance, more efficient design reuse and faster SoC development, leading to lower development and production costs. For more information, visit or find us on LinkedIn at Arteris, ArterisIP, FlexNoC. Ncore, PIANO, and the ArterisIP logo are trademarks of Arteris, Inc. All other product or service names are the property of their respective owners. About iNoCs iNoCs, incorporated in 2007, is a supplier of Network-on-Chip (NoC) technologies. Spun off of the Federal Polytechnic School of Lausanne (EPFL), Switzerland, it brings to the market algorithms and IP based on pioneering academic research since 2003. In particular, iNoCs commercializes technology for automated interconnect synthesis. For more information, contact

Jan 1st, 2010

iNoCs Joins EU Project NaNoC
Project to Advance NoC State-of-the-Art
Lausanne, Switzerland (January 1st, 2010) — iNoCs announced today that it has joined the project NaNoC, sponsored by the European Union. The project includes among its members Infineon and Lantiq, Germany; Teklatech, Denmark; Simula, Norway; the Polytechnical University of Valencia, Spain; the University of Ferrara, Italy. The project is aimed at creating novel NoC design toolchains with superior capabilities in terms of Quality of Service, power management, fault tolerance, physical effect awareness, reconfigurability, virtualization, and integration of heterogeneous cores. More information at the project website.

Jan 26th, 2009

iNoCs Announces Appointment of New CEO
Industry Veteran Massimo Vanzi Joins iNoCs
Lausanne, Switzerland (January 26th, 2009) — iNoCs announced today that Massimo Vanzi has been named Chief Executive Officer, effective immediately. Massimo replaces Federico Angiolini, who has served as CEO since the company incorporation in 2007. Federico Angiolini will continue his commitment to the iNoCs mission in the position of Vice President of Engineering.

"Massimo Vanzi brings to iNoCs extensive experience in the EDA industry," said Giovanni De Micheli, co-founder of iNoCs and professor at EPFL, Switzerland. "Massimo's leadership skills and expertise in chip design make him the right CEO to lead iNoCs to success, making him the ideal candidate to pursue expansion into markets such as consumer electronics, automotive and telecommunications," added Prof. De Micheli.

"I am very pleased to join iNoCs," said Massimo Vanzi. "iNoCs is a young company with very promising technology and a brilliant future ahead. The founding team of iNoCs is composed of some of the most talented experts in on-chip interconnects from the academia, and I firmly believe that iNoCs products are innovative and can be met with significant industry adoption."

"It is thrilling to welcome Massimo to our company," added Dr. Federico Angiolini, also co-founder of iNoCs, who previously held the CEO position. "Massimo is the right professional to bring our offering and organization to the next level of customer satisfaction. I will be happy to work with him focusing on the continued improvement of our technology as VP of Engineering."

Massimo Vanzi is a highly experienced manager with over 30 years of background in the semiconductor and EDA industries. After earning his Dr. Eng. degree in electronics in 1976 from the University of Genoa (Italy) and his Master’s of Science degree in Electrical Engineering and Computer Science in 1979 from Stanford University (California), Massimo worked with Signetics Inc. in Sunnyvale, Calif., doing research on semiconductor devices, and then joined SGS-Thomson in 1980. From 1980 to 1993 Massimo took several responsibilities in STMicroelectronics including definition, development and support of the unified ASIC design flow and design libraries/PDK environment for the whole ST Group, definition and support of the Corporate ASIC design methodology and realization of several advanced ASIC designs for ST customers. In 1993 Massimo founded Accent S.r.L. with the support of Cadence Design Systems Inc. and STMicroelectronics S.r.l. In Accent Massimo had the role of General Manager from 1994 to 2005, transforming a small startup of five engineers into the leader IC design and fabless ASIC Company in Europe and one of top 20 in the world. In early 2006 Massimo completed an LBO process while becoming CEO and shareholder of the new Accent S.p.A.

In October 2008 Massimo left Accent International SA, while remaining shareholder of the company and started his own business on advising and supporting high-tech startups and SME’s to define their own company and product strategy. Massimo is also co-founder and shareholder of Genova High Tech and member of the Italian Angels for Growth organization to support birth of innovative high-tech startups in Italy.

iNoCs - Structured Interconnects
iNoCs provides developers of advanced chips based on the integration of heterogeneous cores with the most innovative combination of tools and IP for the automatic synthesis of on-chip interconnects. iNoCs's offering allows customers to achieve interconnect design closure in state-of-the-art and future lithography processes, improving product performance and time-to-market. iNoCs is based in Lausanne, Switzerland. More information at or at
© 2009 iNoCs.

This news release contains forward-looking statements regarding iNoCs technologies and future performance that are subject to risks and uncertainties. These risks and uncertainties could cause actual results to differ materially from those described in such statements. The reader is cautioned not to rely unduly on these forward-looking statements, which are not a guarantee of future or current performance. Such risks and uncertainties include long-term program commitments, the performance of third parties, the sustained performance of current and future products, financing risks, the ability to integrate and support a complex technology solution involving multiple providers and users.

May 7th, 2008

Venture 08, Zuerich, Switzerland
iNoCs is selected among the Top 20 start-ups in Switzerland by the Venture 08 panel based on its business plan. Venture 08 is a business competition sponsored by McKinsey and ETHZ, Switzerland.

Jan 24th, 2008

Venture Kick, Bern, Switzerland
iNoCs is selected as a winner of the second round of Venture Kick, a start-up incentive program where start-ups are offered prize money and coaching by a team of experts.

Jun 12th-22nd, 2007

Venture Leaders, Boston, MA, USA
iNoCs is selected out of about 100 projects as one of only 20 Swiss start-ups eligible for free a ten-day business coaching stage at Babson College in Boston.